Get the most benefit from your DDR4 and next generation memory designs.
By Ailee Grumbine, Strategic Product Planner, Keysight Technologies, Inc.
DDR4 DRAM technology with fast data rates of 1,600 MT/s and higher, forced industry to adopt high speed serial interface testing methodologies. Traditional setup and hold time tests are now replaced with eye diagrams and mask tests to account for bit error rate. Many DDR4 designers are still spending a lot of time trying to understand the specification and translate them into measurement methodologies. DDR5 is the next generation memory after DDR4, offering speeds up to 6.4 GT/s, and DDDR5 will present more design and testing challenges than DDR4. This article will help designers to better understand the DDR4 specification and its testing methodologies to help them prepare for the migration to DDR5.
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When To Take The Leap – The Technology
There are many factors that drive technology migration. It helps to know the technology availability, the application, the speed, and the power requirement. There are three classes of volatile memory that are optimised for the different classes of applications – computer/server, graphics, and mobile applications. DDR4 is designed for the computing and server industry and has been around for quite some time with the fastest defined speed at 3.2 GT/s. JEDEC is currently working on the next generation DDR memory, DDR5, to fulfil the request for faster data rates.
It is anticipated that DDR5 will be able to operate up to 6.0 GT/s or higher. Graphics memory has the highest operating speed now at above 5.0 GT/s. GDDR6 is the latest graphics memory technology. The last class of volatile memory is the mobile DRAM which is dominated by low power DRAM using DDR technology. LPDDR4 speed now surpasses DDR4 speed at 4.2 GT/s.
DDR4 Specification And Measurement Methods
JEDEC DRAM specifications are defined at the balls of the DRAM package. This is very different than other high-speed serial interfaces. For the longest time, DDR technology has adopted conservative design specifications. DDR technology uses a bi-directional, singled ended, parallel bus. The specification is written to focus on interconnect and signal integrity characteristics with negative margin for timing budget. The industry over-designs the parts to account for the negative timing margin.
One of the new measurements in DDR4 specification is receiver input masks. This one test would replace the traditional setup and hold time test. Memory timing specifications for previous DDR technologies, like DDR2 and DDR3, were based on assumptions that the data capture will be error free if the data setup and hold time meets the specification. Lower data transfer rates in DDR2 and DDR3 have worked with these assumptions. This is not true for DDR4. DDR4 reflects the fact that random jitter and bit error rate are important parts of the specification and changes have been made to the specification to help address these issues.
Additionally, the specification now includes noise considerations, such as the effect of noise reducing eye openings. With all these specifications added to the standard, the lost margin can now be regained and designers now can simplify their design and reduce design cycles, ultimately saving cost.
The Next Generation Memory
As previously mentioned, the next generation DDR memory is anticipated to have data rates up to 6.5 GT/s. A potential consequence of running at these speeds is that the data eye could be closed at the receiver. This behaviour is observed with other high-speed serial interfaces, such as PCI Express Gen 3. PCI Express Gen 3 implemented equalisation on the receiver to open the eye for measurement and de-emphasis on the receiver side.
The same methodology can be applied to DDR5 technology, with several modifications. Memory is crosstalk dominant unlike PCIE which is loss dominant. Memory is a single ended, parallel bus and not a differential serial bus. The data bits in the DDR memory are not aligned. There is also no loopback mode in DDR4 so there is no way to perform receiver test.
In DDR5, the receiver would need to tune itself via training mode to minimise bit error rate. The specification describes what happens at the ball of the device. If you have an equaliser, the specification is written at the output of the equaliser which is inside the DRAM die. You don’t know if you have an open eye in the die because you can’t probe inside the die directly. Hence, there is no eye mask specification at the ball. The eye would need to be opened using a decision feedback equaliser. The specification would model the impulse response of the channel.
A decision feedback equaliser would back away impulse response effects of the channel which would generate inter-symbol interference. These DDR5 measurements can be made using a scope with BER contour extrapolation. A loopback signal inside the memory would be required to figure out the receiver mask the memory would require.
Putting It All Together
There are key components that are required to ensure success of implementing DDR5 memory designs. Test equipment like oscilloscopes and bit error rate testers could help with some of the measurement challenges. Being able to make the measurement accurately would require advance BGA probing capabilities as the DRAM package is a BGA component. Parasitic loading is a big challenge to overcome when probing these high-speed buses.
Early design stages could benefit from using modern simulation tools to model and optimise the system design. Power measurements are also a challenge given that the specification itself is not clear on how much noise is allowed in the power rail.
In summary, understanding the technology and the specification helps you explore the best options for your design implementation. DDR4 memory is the first technology to adopt the receiver input mask concept. Understanding of this concept allows user to quickly make meaningful measurements to ensure that the design works.
DDR5 memory is the most advanced memory technology in its class. Measurement challenges associated with this new technology can be addressed using high-speed serial standard measurement techniques like equalisation. A well thought out approach to the measurement requirement will enable high confidence in your memory system design.