Keysight Technologies, Inc., National Information Optoelectronics Innovation Center (NOIEC) and CompoundTek, will work together to establish layout design standards for the automated testing of photonic integrated circuits (PICs).
PICs offer a multitude of advantages over their discrete components and bulk optics counterparts including significant footprint reduction, improved stability and lower energy consumption. PICs are ubiquitous in telecommunication networks solutions and attract increasing attention in new applications like sensing, bio-medical, cryptography and quantum computing. As the range of applications widens, a high level of standardisation and automation becomes essential to ensure the scalability, process monitoring and yield required for volume production.
Keysight, NOEIC and CompoundTek will collaborate to establish a globally recognised standardised approach to PIC layout, enabling access to automated testing, generic assembly and packaging services for scaling to volume production. The goal is to interface with PIC designers who define the test protocols during the design stage and with the test facilities which will enable automation and define measurement procedures and their parameters.
The consortium will work together to standardise PIC layout conventions and design rules for edge-coupled circuits, which include, but are not limited to, die orientation, location of I/O ports, placement of DC pads, fiducials and indication of restricted areas important for automated testing, assembly and packaging. Adopting and deploying a proven integrated solution, featuring Keysight’s Photonic Suite on a fully automated probe station with speed optimised test executive algorithm, facilitates high throughput testing. It also enables Design-For-Test (DFT) and First-Design-Right (FDR) techniques to reduce overall costs associated with the test. Keysight’s Photonic Suite is comprised of Keysight’s PathWave and Photonic Application solutions.
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