The new vertical device architecture demonstrates path to scaling beyond nanosheet, which can enable 85 percent energy reduction compared to scaled finFET transistors.
IBM and Samsung Electronics unveil semiconductor breakthrough that defies conventional design utilising a new vertical transistor architecture that demonstrates a path to scaling beyond nanosheet, and has the potential to reduce energy usage by 85 percent compared to a scaled fin field-effect transistor (finFET)1. The global semiconductor shortage has highlighted the critical role of investment in chip research and development and the importance of chips in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.
The new vertical transistor breakthrough could help the semiconductor industry continue its relentless journey to deliver significant improvements, including:
- Potential device architecture that enables semiconductor device scaling to continue beyond nanosheet.
- Cell phone batteries that could go over a week without being charged, instead of days.
- Energy intensive processes, such as cryptomining operations and data encryption, could require significantly less energy and have a smaller carbon footprint.
- Continued expansion of Internet of Things (IoT) and edge devices with lower energy needs, allowing them to operate in more diverse environments like ocean buoys, autonomous vehicles, and spacecraft.
“Today’s technology announcement is about challenging convention and rethinking how we continue to advance society and deliver new innovations that improve life, business and reduce our environmental impact,” said Dr. Mukesh Khare, vice president of hybrid cloud and systems at IBM Research. “Given the constraints the industry is currently facing along multiple fronts, IBM and Samsung are demonstrating our commitment to joint innovation in semiconductor design and a shared pursuit of what we call ‘hard tech.'”
Historically, transistors have been built to lie flat upon the surface of a semiconductor, with the electric current flowing laterally, or side-to-side, through them. With new Vertical Transport Field Effect Transistors, or VTFET, IBM and Samsung have successfully implemented transistors that are built perpendicular to the surface of the chip with a vertical, or up-and-down, current flow.
The VTFET process addresses many barriers to performance and limitations as chip designers attempt to pack more transistors into a fixed space. It also influences the contact points for the transistors, allowing for greater current flow with less wasted energy. Overall, the new design aims to deliver a two times improvement in performance or an 85 percent reduction in energy use as compared to scaled finFET alternatives1.
1 VTFET nanosheet and scaled FinFET device simulation results are compared at the same footprint and at an aggressive sub-45nm gate pitch. VTFET nanosheets provides ~ 2X performance of the scaled FinFET at equivalent power due to VTFET maintaining good electrostatics and parasitics while FinFET performance is impacted by severe scaling constraints. Or VTFET could provide as much as 85% power reduction compared to the scaled FinFET architecture as compared at an equivalent frequency on the extrapolated power-performance curves.
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