Clocks are one of the most important signals in modern chipset and device design. As the reference signal, the quality of a clock affects the system performance in terms of Bit Error Rate (BER). Article by Yang Zou, Wireless Devices & Operators Senior Business and Solution Manager, Keysight Technologies, Inc.
Clocks are one of the most important signals in modern chipset and device design. As the reference signal, the quality of a clock affects the system performance in terms of Bit Error Rate (BER). A key measurement of Clock signal quality is phase noise. Phase noise is the characteristic of frequency stability of a signal, which is defined as the degree to which an oscillating source produces the same frequency throughout a specific period. Frequency stability consists of two components: long term and short term. This article will illustrate the advantages of test methodologies to measure clock phase noise and help engineers decide which approach best fit for their specific test requirement.
In modern high-speed digital design, the clock signal is the ultimate source of system timing. Clock is used to time logic transitions in the transmitter and set the sampling positions at the receiver. The reference clock can be recovered from the transmitted serial data in an undistributed clock system or transmitted as a separate signal in a distributed clock system. The clock is reproduced in the clock recovery circuit, for example a PLL, at the receiver from reference clock.
A clock signal originates from an oscillator system. An electric oscillator could be described as an RLC circuit as figure 1.
For a good electrical oscillator, ωR, resonance frequency is 1/√LC and damping factor ζ is R/2L. The bandwidth is proportional to the damping factor and the quality is the ratio of the resonant frequency to the bandwidth, which is inversely proportional resistance. The quality of an oscillator is a measure of how sharply peaked the response curve is. Most crystal oscillators for telecom, such as 5G system are between 104 and 106. Per a public paper, 475.5MHz XO was already developed for millimeter wave(mmW) applications, which is 30G to 300GHz applications such as 5G or 802.11AY.
An ideal oscillator would have infinite quality, which is zero bandwidth. Theoretically possible to implement in a superconductor, not realistic for industry. An ideal oscillator can be characterised as:
A real oscillator always includes amplitude noise and phase noise .
Unfortunately, phase noise can’t be eliminated or reduced by applying a filter.
The basic concept of phase noise involves frequency stability, which is defined as the degree to which an oscillating source produces the same frequency throughout a specific period. There are many ways to determine and quantify phase noise. The most common one is single side-band phase noise, L(t), defined by US National Institute of Standard and Technology (NIST) as “The ratio of the power density at an offset frequency from the carrier to the total power of the carrier signal”.
Phase noise in frequency domain is characterized by Sφ (f), compared to frequency spectrum density of the clock, S(f), instead of square of the Fourier transform of the signal spectrum density, it’s the square of the Fourier transform of the phase noise. The phase noise frequency domain fφ, is related to the signal frequency domain f by fφ=f- fC. L(t), single side-band phase noise as described in last paragraph is defined by L(t)≈1/2 Sφ (f) .
Clock performance is critical to the system performance. Clock jitter is usually used to measure the quality of a clock. Clock jitter is analysed under system-specific assumptions. For example, the restrictive requirement of PCIe Gen 5 is different compared to SATA or USB 3.1. Clock jitter reflects on BER under different limitations. Traditional clock specifications like peak-to-peak phase jitter, period jitter, and cycle-to-cycle jitter indicate clock quality, but don’t answer the only truly relevant question: Will the clock work in the system you are designing?
The most useful measurement of clock quality is the phase noise spectrum. A simple way to determine if a clock is adequate for an application is to apply a mask test to the phase noise spectrum. By requiring the phase noise fit under a mask, the amount of phase noise in different offset frequency bands can be limited.
Traditional ways to measure phase noise are direct spectrum, phase detector, and cross correlation.
One of the simplest methodologies to measure the phase noise, if the inherent phase noise SSB of equipment at offset is significantly lower than the signal phase noise L(t). The connection is very simple. The signal is directly connected to a signal analyser/spectrum analyser and most of signal analyse software will conduct the analysis work.
Phase noise can be performed by using a phase detector to remove the carrier and the phase noise signal from a golden clock or reference clock by shifting 90 degrees. After a mixer and low passband filter (LPF) with a low noise amplifier, the signal analyser will convert the result into phase noise. This method provides great sensitivity and wide measurement coverage. The methodology is not sensitive to amplitude noise. The system block diagram can be illustrated as figure 2.
There are several different ways to implement a phase detector under the same concept. Such as the PLL method, which provides a golden clock from the feedback circuit after LPF and a Phase Lock Loop (PLL). Another methodology is analogue delay line, which splits the input clock, on one path it passes through a delay line and the other path is shifted 90 degrees. The two results are mixed or a digital discriminator method is used to handle the date in a DSP system.
To minimise the impact of internal noise generated by equipment channels, the DUT noise passes through multiple correlated channels. Noise from the clock is coherent and not affected by cross-correlation. The noise generated by each channel is incoherent which is eliminated by the cross-correlation system. The architecture provides supreme measurement sensitivity without requiring exceptional performance hardware to reach excellent measurement results.
The architecture can be illustrated as figure 3. To have the best test result, the most accurate clock sources could be applied in this diagram and metrology level accuracy can be reached. It will be a high performance and high cost solution.
Rapidly evolving mobile devices, networks, and data centres make cellular site synchronisations more challenging. 5G applications such as massive MIMO, small cells, MDAS, RRH, BBU, and fronthaul demand improved phase and frequency accuracy. Optimised timing solutions and accurate clock sources to support millimetre wave (mmWave) are expected. Beside accuracy, the quality of the clock generator under higher CW and higher bandwidth characterisation becomes critical.
PCIe as one of the most important high-speed digital buses, allows the user to use spread-spectrum clocking (SSC) to avoid electromagnetic interference (EMI) at specific frequency by modulating clock with another low frequency signal. It also brings more challenges regarding phase noise analysis of the modulated clock.
Traditional ways to measure the clock phase noise are facing the challenges of frequency and offset range, as well being required to support SSC enabled clock. Using a scope to measure phase noise has become a viable alternative.
Sampling scopes were first considered due to their extremely clean phase noise floor. For example, Keysight 86100D and N1000A are high performance instruments, with intrinsic jitter between 50 to 100 fs. Viable for many applications, except wide offset cases, where the maximum offset might not be sufficient.
In the past, real-time scopes were not used because the jitter noise floor was higher than other solutions. However, the intrinsic jitter of real-time scopes has improved significantly in recent years. The Keysight Z series scope has 50 fs intrinsic jitter and the new Keysight UXR is even lower at 25 fs.
Real-time scopes with low intrinsic jitter and a noise reduction methodology can measure the phase noise of clocks accurately. As figure 4 illustrates, both polarities of differential signals from a PCIe evaluation board were connected directly into two channels of a scope. Figure 5 compares the conventional method (purple waveform), noise reduction method on a real-time scope (green waveform), and industry standard phase noise test equipment SSA (E5052B from Keysight technologies, yellow waveform). Noticeably, the noise reduced method offers results comparable to the industry standard.
In this article, we discussed clock quality and different technologies to characteristic phase noise, one of the most important parameters of clock quality. The advantage of conventional methods such as direct spectrum, phase detector, and cross-correlated were covered. However, 5G technologies and SSC enabled clocks demand the higher frequency and bandwidth than conventional methods provide. Real time scopes now provide viable solutions for phase noise measurements. Further improvements in accuracy, bandwidth, and reduction in test time are expected to continue to meet dynamic industry requirements.
CHECK OUT OUR LATEST ISSUE!
WANT MORE INDUSTRY INSIGHTS? SUBSCRIBE TO IAA NOW!